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e preliminary ma y 1999 order number: 290546-006 n low-cost linear flash card n single supply: 5 volt operation n fast read performance ? 100 ns maximum access time (2-, 4-, 8-mbytes) ? 150 ns maximum access time (16-mbytes) n x16 data interface n high-performance random writes ? 8 m s typical word write n automated program and erase algorithms ? 28f008sa command set n state-of-the-art 0.4 m m etox? v flash technology n 100,000 erase cycles per block n 64-kword blocks n pc card standard type 1 form factor the intel ? value series 100 card offers a low cost removable solid-state storage solution for code and data storage, high-performance disk emulation, and applications in mobile pcs and dedicated embedded applications. manufactured with intel ? flashfile? memory, this card takes advantage of a revolutionary architecture that provides innovative capabilities, automated program/erase algorithms, reliable operation and very high read/write performance. the flash memory card provides one of the lowest cost, highest performance nonvolatile read/write solutions for solid-state storage applications. these applications are enhanced further with this products symmetrically-blocked architecture, extended mtbf, and 5 volt operation. the flash memory card can be used as a simple x16 linear array of flash devices. the pc card form factor offers an industry-standard pinout, removable linear flash memory, and the ability to upgrade system memory software without changing the board layout. note: this document formerly known as value series 100 flash memory card 2-, 4-, 8-, 16 megabytes . 5 volt value series 100 flash memory card imc002flsc, imc004flsc, imc008flsc, imc016flsc
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the imc002flsc, imc004flsc, imc008flsc, imc016flsc may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 5937 denver, co 80217-4725 or call 1-800-879-4683 or visit intels website at http://www.intel.com copyright ? intel corporation 1997, 1998, 1999 cg-041493 *other brands and names are the propert y of their respective owners
e imc002/004/008/016flsc 3 preliminary contents page page 1.0 scope of document .................................5 2.0 product overview ...................................5 3.0 value series 100 card architecture overview.....................................................5 3.1 card pinout and pin description...................5 4.0 card control logic..............................10 4.1 bus operations ..........................................10 4.1.1 read....................................................10 4.1.2 output disable.....................................10 4.1.3 standby ...............................................10 4.1.4 intelligent identifier operation ..............10 4.1.5 write ....................................................10 4.2 address decode logic ...............................11 4.3 data control ...............................................11 5.0 command definitions ............................12 5.1 read array command (ffffh) .................12 5.2 intelligent identifier command (9090h) ......12 5.3 read status register command (7070h) ..13 5.4 clear status register command (5050h) ..13 5.5 erase setup/erase confirm commands (2020h, d0d0h)........................................14 5.6 erase suspend/erase resume commands (b0b0h, d0d0h).......................................15 5.7 program commands (4040h or 1010h) .....15 5.8 word write suspend command .................15 5.9 set block lock-bit command .....................15 5.10 clear block lock-bits command ..............16 6.0 pc card information structure ..... 16 7.0 system design considerations........ 19 7.1 power supply decoupling.......................... 19 7.2 power-up/down protection........................ 19 7.3 rdy/bsy# and program/block erase polling ...................................................... 19 7.4 v cc , v pp , reset transitions and the command/status registers ...................... 19 8.0 electrical specifications................. 20 8.1 absolute maximum ratings ....................... 20 8.2 operating conditions ................................. 20 8.3 capacitance .............................................. 20 8.4 dc characteristics..................................... 21 8.5 ac characteristics..................................... 22 8.5.1 read operations: common memory... 22 8.5.2 write operations: common memory ... 24 8.5.2 power-up/power-down....................... 26 8.6 erase and data write performance ........... 27 9.0 packaging ................................................ 28 10.0 ordering information ....................... 29 11.0 additional information .................... 29
imc002/004/008/016flsc e 4 preliminary revision history date of revision version description 02/29/96 -001 original version 01/23/97 -002 added specifications for 16-mbyte card added 16-mbyte tuples added i ccsl for 16-mbyte card changed a 24 from n.c. to active changed interface to cmos only Cremoved table 9.3 ttl interfacing changed dc specification and text to reflect conversion to the 28f0xxs5 family 06/15/97 -003 changed timing specifications for 16-mbyte card added 24- and 32-mbyte cardsthey use the 28f016s5 component changed components used in 4-, 8- and 16-mbyte densities to 28f016s5 changed components used in 2-mbyte density to 28f008s5 increased i ccmax decreased i ccs added block locking and program suspend 12/01/97 -004 removed 24- and 32-mbyte cards changed title bullet to identify two speed versions (100 & 150 ns) for fast read performance based on memory density corrected revision -003 revision history by changing component references in section 2.0, added a reference to figure 1 clarified section 3.0 wording relating to concurrent operations with multiple components altered figure 1 to show a 22 as the least significant card address signal to the card control logic in table 7.0 at location 74h of cis memory changed the value from 33h to 32h for the 32-mb card in section 8.1 (absolute maximum ratings) changed the lower limit of the supply voltage range from C0.5 v to C0.2 v in note 2 of section 8.1 (absolute maximum ratings) removed 20 ns overshoot and undershoot specifications altered note references and added note 4 to the dc characteristics table of section 8.4 changed the specified v cc standby current and v cc sleep current values in the dc characteristics table of section 8.4 added a specification for t phwl (power-down recovery to we# going low) to the common memory write timing table of section 8.5.2 removed the write protect switch item and details from the figure in section 9.0 as a non-material change, clarified or corrected various defective or ambiguous wording 12/01/98 -005 changed name of document from value series 100 flash memory card 2-, 4-, 8-, 16 megabytes 05/06/99 -006 changed references of reset pin to rst pin.
e imc002/004/008/016flsc 5 preliminary 1.0 scope of document this datasheet provides a card architecture overview, all ac and dc characteristics and command definitions. 2.0 product overview the 2-mbyte card consist of two 28f008s5 flash memories. the 4-, 8-, or 16-mbyte cards consist of two, four, or eight 28f016s5 flash memories. figure 1 provides a functional block diagram of the 16-mbyte card. all 28f008s5 and 28f016s5 memory components (referred to herein by the generic 28f0xxs5 part number) are made up of 64-kbyte, individually erasable blocks. therefore, the 2-, 4-, 8-, or 16-mbyte cards contain 32, 64, 128 or 256 independently-erasable, 64-kbyte blocks. when accessed as 16-bit words, the blocks appear to be 128 kbytes. the high byte is in one 64-kbyte block, the low byte in another. in this mode, the 2-, 4-, 8-, or 16-mbyte cards contain 16, 32, 64, or 128, independent 128-kbyte blocks. at the device level, internal algorithm automation allows execution of program and erase operations using a two-program command sequence. the automated program/erase algorithms ensure that data is reliably written in the least amount of time. the memory card interface supports the pc card standard, supported by personal computer memory card industry association (pcmcia) and japanese electronics industry development association (jeida) 68-pin card format. the value series 100 card meets all pcmcia/jeida type 1 mechanical specifications. 3.0 value series 100 card architecture overview a value series 100 card is an array of flash memory devices in a pc card form factor. pairs of 28f008s5 or 28f016s5 (28f0xxs5) devices, connected in parallel, provide lower and upper bytes of a 16-bit access. typical flash memory components only support a single operation at a time. only one block in a 28f0xxs5 can be erased, or only one location programmed, at a time. since a value series 100 contains multiple devices, it is possible to perform multiple concurrent operations in the card. a location in one component can be read while a location in another component is being programmed. (however, all dc characteristics presented herein assume that only one operation is being performed at a time, and that all other components on the card are in stand-by.) a user algorithm which would rely on a memory array based on a specific memory component capacity would be incompatible among all card types and component selections. in the future, the value series may use higher capacity memory devices. therefore, algorithms that are based on a particular organization may not be compatible with these newer, more cost-effective cards. the card information structure (cis) for the value series 100 card is stored in block 0 of the flash memory to reduce the attribute memory cost overhead of an eeprom or asic. in embedded applications, a cis may not be required by the system and the entire memory array can be used by the system. 3.1 card pinout and pin description the 68-pin pc card format provides the system interface for the value series 100 card (see tables 1 and 2). the detailed specifications for this interface are described in the pc card standard specification. the value series 100 card product family conforms to the pinout requirements of pcmcia versions release 1.0, release 2.0 and release 2.01 as well as the pc card standard.
imc002/004/008/016flsc e 6 preliminary d<15:0> a<21:1> we# oe# rst wait# rdy/bsy# wp card control logic d<15:8> d<7:0> a<20:0> zwe# zoe# zry/zby# zrp# bvd 1 28f016s5 device 7 d<7:0> a<20:0> we# oe# rp# ce# ry/by# 28f016s5 device 5 d<7:0> a<20:0> we# oe# rp# ce# ry/by# 28f016s5 device 3 d<7:0> a<20:0> we# oe# rp# ce# ry/by# 28f016s5 device 1 d<7:0> a<20:0> we# oe# rp# ce# ry/by# 28f016s5 device 6 d<7:0> a<20:0> we# oe# rp# ce# ry/by# 28f016s5 device 0 d<7:0> a<20:0> we# oe# rp# ce# ry/by# 28f016s5 device 2 d<7:0> a<20:0> we# oe# rp# ce# ry/by# 28f016s5 device 4 d<7:0> a<20:0> we# oe# rp# ce# ry/by# zce#<7:0> v pp2 v pp1 v ss vs 1 vs 2 cd 2 # cd 1 # bvd 2 ce 1 # ce 2 # open a<25:a22> v cc v pp v ss v cc v pp v ss v cc v pp v ss v cc v pp v ss v cc v pp v ss v cc v pp v ss v cc v pp v ss v cc v pp v ss v cc v cc v ss 0491_01 figure 1. 16-mbyte flash memory card block diagram showing major functional elements
e imc002/004/008/016flsc 7 preliminary table 1. value series 100 card signals pin signal i/o function active pin signal i/o function active 1 gnd ground 27 a 2 i address bit 2 2dq 3 i/o data bit 3 28 a 1 i address bit 1 3dq 4 i/o data bit 4 29 a 0 i address bit 0 4dq 5 i/o data bit 5 30 dq 0 i/o data bit 0 5dq 6 i/o data bit 6 31 dq 1 i/o data bit 1 6dq 7 i/o data bit 7 32 dq 2 i/o data bit 2 7ce 1 # i card enable 1 low 33 wp o write protect high 8a 10 i address bit 10 34 gnd ground 9 oe# i output enable low 35 gnd ground 10 a 11 i address bit 11 36 cd 1 # o card detect 1 low 11 a 9 i address bit 9 37 dq 11 i/o data bit 11 12 a 8 i address bit 8 38 dq 12 i/o data bit 12 13 a 13 i address bit 13 39 dq 13 i/o data bit 13 14 a 14 i address bit 14 40 dq 14 i/o data bit 14 15 we# i write enable low 41 dq 15 i/o data bit 15 16 rdy/bsy# o ready/busy low 42 ce 2 # i card enable 2 low 17 v cc supply voltage 43 vs 1 o voltage sense 1 n.c. 18 v pp1 supply voltage n.c. 44 rfu reserved 19 a 16 i address bit 16 45 rfu reserved 20 a 15 i address bit 15 46 a 17 i address bit 17 21 a 12 i address bit 12 47 a 18 i address bit 18 22 a 7 i address bit 7 48 a 19 i address bit 19 23 a 6 i address bit 6 49 a 20 i address bit 20 24 a 5 i address bit 5 50 a 21 i address bit 21 25 a 4 i address bit 4 51 v cc supply voltage 26 a 3 i address bit 3 52 v pp2 supply voltage n.c.
imc002/004/008/016flsc e 8 preliminary table 1. value series 100 card signals (continued) pin signal i/o function active pin signal i/o function active 53 a 22 i address bit 22 61 reg# i attribute memory select 54 a 2 3 i address bit 23 62 bvd 2 o battery voltage detect 2 55 a 24 i address bit 24 63 bvd 1 o battery voltage detect 1 56 a 25 i address bit 25 n.c. 64 dq 8 i/o data bit 8 57 vs 2 o voltage sense 2 n.c. 65 dq 9 i/o data bit 9 58 rst i reset high 66 dq 10 i/o data bit 10 59 wait# o extend bus cycle low 67 cd 2 # o card detect 2 low 60 rfu reserved 68 gnd ground
e imc002/004/008/016flsc 9 preliminary table 2. value series 100 card signal description symbol type name and function a 0 Ca 25 input address inputs: a 0 through a 25 enable direct addressing of up to 64 mb of memory on the card. signal a 0 is not decoded since the card is x16 only. the memory will wrap at the card density boundary. the system should not try to access memory beyond the cards density, since the upper addresses are not decoded. dq 0 Cdq 15 input/ output data input/output: dq 0 through dq 15 constitute the bi-directional data bus. dq 15 is the most significant bit. ce 1 #, ce 2 # input card enable 1 & 2: ce 1 # enables even byte accesses on d 0 C7 , ce 2 # enables odd byte accesses on d 8C15 . cannot access odd bytes on d 0C7 . oe# input output enable: active low signal enabling read data from the memory card. we# input write enable: active low signal gating write data to the memory card. rdy/bsy# output ready/busy output: indicates status of internally timed erase or program activities. a high output indicates the memory card is ready to accept accesses. cd 1 #, cd 2 # output card detect 1 & 2: these signals provide for card insertion detection. the signals are connected to ground internally on the memory card, and will be forced low whenever a card is placed in the socket. the host socket interface circuitry shall supply 10k or larger pull-up resistors on these signal pins. wp output write protect: this signal is pulled low for pc card standard compatibility. the flash memory card has no wp signal functionality. v pp1 ,v pp2 n.c. program/erase power supply: these power signals are not connected for the 5 v-only card. v cc card power supply: 5.0 v for all internal circuitry. gnd ground for all internal circuitry. reg# input register select: the memory card has no separate attribute memory. the cis is located in common memory. reg# is unconnected on the card. rst input reset: the card is placed in power-on default state when rst is low. rst high is the power-down signal for the memory array. wait# output wait: (extended bus cycle) this signal is pulled high for compatibility. bvd 1 , bvd 2 output battery voltage detect: these signals are pulled high to maintain sram card compatibility. vs 1 , vs 2 output voltage sense: notifies the host socket of the cards v cc requirements. vs 1 and vs 2 are open to indicate a 5 v, 16-bit card has been inserted. rfu reserved for future use n.c. no internal connection to card pin may be driven or left floating.
imc002/004/008/016flsc e 10 preliminary 4.0 card control logic 4.1 bus operations flash memory reads, erases and programs are performed using bus cycles to or from the flash memory that conform to standard microprocessor bus cycles. 4.1.1 read the components on the value series 100 card have three read modes: read memory array, read intelligent identifier or read status register; they are enabled by writing the appropriate read mode command to the command user interface (cui). the 28f0xxs5 automatically resets to read array mode upon initial device power-up, or after reset. the 28f0xxs5 has four control pins, two of which must be logically active to obtain data at the outputs. chip enables (ce 1,2 #) are the device selection control, and, when active, enable the selected memory device. output enable (oe#) is the data input/output (dq 0 Cdq 15 ) direction control, and, when active, drives data from the selected memory onto the i/o bus. we# must be driven to v ih during a read access. 4.1.2 output disable with oe# and we# at a logic-high level (v ih ), the device outputs are disabled. output (dq 0 Cdq 15 ) are placed in a high-impedance state. 4.1.3 standby ce 1,2 # at a logic-high level (v ih ) places the card in standby mode. standby operation disables much of the cards circuitry and substantially reduces device power consumption. the outputs (dq 0 Cdq 15 ) are placed in a high-impedance state independent of the status of oe#. if the card is de-selected during program or block erase, the card will continue functioning and consuming normal active power until the operation completes. 4.1.4 intelligent identifier operation the intelligent identifier operation outputs the manufacturer code, 89h, and the device code: a2h, a6h or aah. the table below lists the device and capacity for each device code. device code device type component capacity a2h 28f008sa 1 mb a6h 28f008s5 1 mb aah 28f016s5 2 mb a system s hould recognize all three codes in order to support current cards, based on the 28f008sa and newer cards based on the 28f0xxs5 family. the manufacturer and device codes are read via the cui. following a write of 9090h to the cui, a read from address location 0000h outputs the manufacturer code (8989h). a read from address 0002h outputs the device code: a2a2h, a6a6h, or aaaah. future cards may incorporate devices that implement the common flash interface (cfi). this standard supports forward and backward compatibility between flash memories. new algorithms should first determine if the card is cfi compliant, and if it is not, then read the intelligent identifiers. 4.1.5 write writes to the cui enable reading of device data and intelligent identifiers. they also control inspection and clearing of the status register. the contents of the interface register serves as input to the internal state machine on each component. the cui itself does not occupy an addressable memory location. the interface register is a latch used to store the command, address and data information needed to execute the command. erase setup and erase confirm commands require both appropriate command data and an address within the block to be erased. the program setup command requires both appropriate command data and the address of the location to be written, while the program command consists of the data to be written and the address of the location to be written.
e imc002/004/008/016flsc 11 preliminary the cui is written by bringing we# to a logic-low level (v il ) while ce# is low. addresses and data are latched on the rising edge of we#. standard microprocessor write timings are used. 4.2 address decode logic the address decode logic selects which components device pair is enabled during a read or write access. unused upper addresses for the value series 100 card will not be decoded. the address decoding will wrap around at the cards density. the value series 100 card does not have a separate attribute memory space and reg# is not included in the address decode logic. reg# accesses will result in a read/write to the common memory flash array. 4.3 data control as shown in table 3, data paths and directions are selected by the data control logic using we#, oe#, ce 1 #, and ce 2 # as logic inputs. the data control logic selects any of the pcmcia word-wide, even - byte and odd -byte modes for either reads or writes to common memory. note: this card has a x16 interface. the odd byte cannot be accessed on the lower data path (d 0 C7 ). a 0 is not decoded. table 3. data access mode truth table mode reset ce 2 #ce 1 # oe# we# a 1 v pp d 8 C15 d 0C7 notes even byte-read v il v ih v il v il v ih x x high-z even 1,2 odd byte-read v il v il v ih v il v ih x x odd high-z 1,2 word-read v il v il v il v il v ih x x odd even 1,2 even byte-write v il v ih v il v ih v il x x xxx even 3 odd byte-write v il v il v ih v ih v il x x odd xxx 3 word-write v il v il v il v ih v il x x odd even 3 manufacturer id v il v il v il v il v ih v il x 89h 89h device id v il v il v il v il v ih v ih x a6h a6h 4 standby v il v ih v ih x x x x high-z high-z output disable v il xxv ih v ih x x high-z high-z power-down v ih x x x x x x high-z high-z notes: 1. refer to dc characteristics . 2. x can be v il or v ih for control pins and address. 3. refer to table 4 for valid d in during a program operation. 4. the device code can be a6h or aah. software should check for all three cases for compatibility with future cards.
imc002/004/008/016flsc e 12 preliminary 5.0 command definitions device operations are selected by writing specific commands into the command user interface. table 4 defines the 28f0xxs5 commands. 5.1 read array command (ffffh) upon initial device power-up, and after reset, the 28f0xxs5 defaults to read array mode. this operation is also initiated by writing ffffh into the cui on the component. microprocessor read cycles retrieve array data. the device remains enabled for reads until the cui contents are altered by issuing a valid command. once the internal wsm has started a byte program or block erase operation, the device will not recognize the read array command until the wsm has completed its operation. 5.2 intelligent identifier command (9090h) the 28f0xxs5 contains an intelligent identifier operation, initiated by writing 9090h into the cui. following the command write, a ready cycle from address 00000h retrieves the manufacturer code of 8989h. a read cycle from address 00002h returns the device code of a2a2h, a6a6h, or aaaah. to terminate the operation, it is necessary to write another valid command into the register. table 4. 28f008sa-compatible mode command bus definitions first bus cycle second bus cycle command r/w addr data r/w addr data read array w da ffffh r da ad intelligent identifier w da 9090h r ia id read status register w da 7070h r da srd clear status register w da 5050h program w pa 4040h w pa pd program (alternate) w pa 1010h w pa pd block erase/confirm w ba 2020h w ba d0d0h erase or program suspend w da b0b0h erase or program resume w da d0d0h addresses: data: da device address ad array data ba block address srd status reg. data ia identifier address id identifier data pa program address pd program data
e imc002/004/008/016flsc 13 preliminary table 5. new commands command bus cycles reqd. first bus cycle second bus cycle r/w addr data r/w addr data set block lock-bit 2 w x 6060h w ba 0101h clear block lock-bits 2 w x 6060h w x d0d0h 5.3 read status register command (7070h) the 28f0xxs5 components on the value series 100 card each contain a status register which may be read to determine when a program or block erase operation is complete, and whether that operation completed successfully. the status register may be read at any time by writing the read status register command (7070h) to the cui. after writing this command, all subsequent read operations output data from the status register, until another valid command is written to the cui. the contents of the status register are latched on the falling edge of oe# or ce#, whichever occurs first. oe# or ce# must be toggled to v ih before further reads to update the status register latch. note: two 28f0xxs5 devices are used in parallel to form a x16 operation. both status registers need to be checked when determining the status of a x16 erase/program operation. 5.4 clear status register command (5050h) the erase status and program status bits are set to 1s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 5). by allowing system software to control the resetting of these bits, several operations may be performed (such as cumulatively writing several bytes or erasing multiple blocks in s equence). the status register may then be polled to determine if an error occurred during that sequence. this status register functionality adds flexibility to the way the device may be used. additionally, the v pp status bit (sr.3) must be reset by system software before further writes or block erases are attempted. to clear the status register, the clear status register command (50h) is written to the cui.
imc002/004/008/016flsc e 14 preliminary table 6. status register definition wsms ess es ps vpps r r r 76543210 sr.7 = write state machine status 1 = ready 0 = busy sr.6 = erase suspend status 1 = erase suspended 0 = erase in progress/completed sr.5 = erase status 1 = error in block erasure 0 = successful block erase sr.4 = program status 1 = error in program 0 = successful program sr.3 = v pp status 1 = v pp low detect, operation abort 0 = v pp ok sr.2 = byte write suspend status 1 = byte write suspended 0 = byte write in progress/completed sr.1 = device protect status 1 = block lock-bit detected, operation abort 0 = unlock notes: rdy/bsy# or the write state machine status bit must first be checked to determine byte write or block erase completion, before the byte write or erase status bit are checked for success. if the program and erase status bits are set to 1s during a block erase attempt, an improper command sequence was entered. attempt the operation again. if v pp low status is detected, the status register must be cleared before another program or block erase operation is attempted. the v pp status bit, unlike an a/d converter, does not provide continuous indication of v pp level. the wsm interrogates the v pp level only after the program or block erase command sequence have been entered and informs the system if v pp has not been switched on. sr.1 does not provide a continuous indication of master and block lock-bit values. the wsm interrogates the master lock-bit, block lock-bit, and rst only after block erase, byte write, or lock-bit configuration command sequences. it informs the system, depending on the attempted operation, if the block lock-bit is set. reading the block lock and master lock configuration codes after writing the read identifier codes command indicates master and block lock-bit status. sr.0 is reserved for future use and should be masked out when polling the status register 5.5 erase setup/erase confirm commands (2020h, d0d0h) erase is executed one block at a time, initiated by the two-cycle comm and sequence. an erase setup command (2020h) is first written to the cui, followed by the erase confirm command (d0d0h). these commands require both appropriate sequencing and an address within the block to be erased to ffffh. block preconditioning, erase and verify are all handled internally by the wsm, invisible to the system. after the two-command erase sequence is written to it, the 28f0xxs5 automatically outputs status register data when read. the cpu can detect the completion of the erase event by analyzing the output data of the rdy/bsy# pin, or the wsm status bit of the status register. when erase is completed, the erase status bit should be checked. if erase error is detected the status register should be cleared. the cui remains in read status register mode until further commands are issued to it.
e imc002/004/008/016flsc 15 preliminary 5.6 erase suspend/erase resume commands (b0b0h, d0d0h) the erase suspend command allows block erase interruption in order to read data from another block of memory. once the erase process starts, writing the erase suspend command (b0b0h) to the cui requests that the wsm suspend the erase sequences at a predetermined point in the erase algorithm. the 28f0xxs5 continues to output status register data when read, after the erase suspend command is written to it. polling the wsm status and erase suspend status bits will determine when the erase operation has been suspended (both will be set to 1). rdy/bsy# will also transition to v oh . at this point, a read array command can be written to the cui to read data from blo cks other t han that which is suspended. the only other valid commands, at this time, are read status register (7070h) and erase resume (d0d0h), at which time the wsm will continue with the erase process. the erase suspend status and wsm status bits of the status register will automatically cleared and the rdy/bsy# will return to v ol . after the erase resume command is written to it, the 28f0xxs5 automatically outputs status register data when read. 5.7 program commands (4040h or 1010h) the program command is executed by a two- command sequence. the program setup command (4040h or 1010h) is written to the cui, followed by a second write specifying the address and data (latched on the rising edge of we#) to be programmed. the wsm then takes over, controlling the program and program verify algorithms internally. after the two-command write sequence is written to it, the 28f0xxs5 automatically outputs status register data when read. the cpu can detect the completion of the program event by analyzing the output of the rdy/bsy# pin, or the wsm status bit of the status register. only the read status register command is valid while program is active. when program is complete, the program status bit should be checked. if program error is detected, the status register should be cleared. the internal wsm verify only detects errors for 1s that do not successfully program to 0s. the cui remains in read status register mode until further commands are issued to it. 5.8 word write suspend command the conversion to the 28f0xxs5 family adds the capability to suspend a programming or word-write operation. once a word write operation is suspended, the card can be read, even if the data is located on the same component as was being programmed. the command to suspend programming is the same as the erase suspend command, b0b0h. the program operation can be resumed by issueing the program resume command, d0d0h. once the word write process starts, writing the word write suspend command requests that the wsm suspend the word write sequence at a predetermined point in the algorithm. after the host writes the word write suspend command, it should write the read status register command. polling status register bits sr.7 and sr.2 can determine when the wsm suspends the byte write operation (both will be set to 1). busy# will also transition to v oh . specification t whrh1 defines the word write suspend latency. it is also possible that the word write completes before the device has an opportunity to suspend. the host should also check for this condition. after the word write has been suspended, the host can write the read array command to read data from any location except the suspended location. the only other valid commands while word write is suspended are read status register and word write resume. after the host writes a word write resume to the cui, the wsm will continue the word write process. status register bits sr.2 and sr.7 will automatically clear and busy# will return to v ol . after the host writes the word write resume command, the device automatically outputs status register data when read. 5.9 set block lock-bit command the host can enable a flexible block locking and unlocking scheme using the set block lock-bit command. this command enables the host to lock individual blo cks within the flash array. the block lock-bits gate program and erase operations.
imc002/004/008/016flsc e 16 preliminary the host sets the block lock-bit using a two-cycle command sequence. the host writes the set block lock-bit setup command along with the appropriate block or device address. this command is followed by the set block lock-bit confirm command (and an address within the block to be locked). the wsm controls the set lock-bit algorithm. after the host completes the command sequence, the card automatically outputs status register data when read. the cpu can detect the completion of the set lock-bit event by analyzing the busy# pin output or status register bit sr.7. when the wsm completes the set lock-bit operation, the host should check status register bit sr.4. if the host detects an error it should clear the status register. the cui will remain in read status register mode until the host issues a new command. this two-step sequence of set-up followed by execution ensures that the host does not accidentally set the lock-bits. an invalid set block lock-bit command will result in the wsm setting status register bits sr.4 and sr.5 to 1. 5.10 clear block lock-bits command the host clears all set block lock-bits in parallel using the clear block lock-bits command. the host is free to clear block lock-bits using the clear block lock-bits command the host executes the clear block lock-bits operation using a two- cycle comm and sequence. the host must first issue a clear block lock-bits setup command. this command is followed by a confirm command. after the host completes the two-cycle comm and sequence, the device automatically outputs status register data when read. the cpu can detect completion of the clear block lock-bits event by analyzing the busy# pin output or status register bit sr.7. when the wsm completes the operation, the host should check status register bit sr.5. if the host detects a clear block lock-bit error, the host should clear the status register. the cui will remain in read status register mode until the host issues another command. this two-step sequence of set-up followed by execution ensures that the host does not accidentally clear block lock-bits. an invalid clear block lock-bits command sequence will result in the wsm setting status register bits sr.4 and sr.5 to 1. if a clear block lock-bits operation is aborted due to v cc transitioning out of valid range or rst active transition, block lock-bit values are left in an undetermined state. the host must repeat the clear block lock-bits command to initialize block lock-bit contents to known values. 6.0 pc card information structure the card information structure (cis) begins at address 00000000h of the cards common memory plane and resides sequentially in memory locations with even byte memory addresses. it contains a variable length chain of data blo cks (tuples) that conform to a basic format (table 6). the cis of the value series 100 card is found in table 7. caution: the cis data in block 0 is not write protected and should not be erased by the system software if the cis is needed for card recognition. table 7. pc card tuple format bytes data 0 tuple code: cistpl_xxx. the tuple code 0ffh indicates no more tuples in the list. 1 tuple link: tpl_link. link to the next tuple in the list. this can be viewed as the number of additional bytes in tuple, excluding this byte. a link field of zero indicates an empty tuple body. a link field containing 0ffh indicates the last tuple in the list. 2-n bytes specific to this tuple.
e imc002/004/008/016flsc 17 preliminary table 8. value series 100 card tuples address value description 00h 01h cistpl_device 02h 03h tpl_link 04h 54h 54h 54h 53h type/speed 2 mb: flash / 100 ns 4 mb: flash / 100 ns 8 mb: flash / 100 ns 16 mb: flash / 150 ns 06h 06h 0eh 1eh 3eh card size: 2 mb 4 mb 8 mb 16 mb 08h ffh end of device 0ah 1eh cistpl devicegeo 0ch 06h tpl_link 0eh 02h dgtpl_bus 10h 11h dgtpl_ebs 12h 01h dgtpl_rbs 14h 01h dgtpl_wbs 16h 03h dgtpl_part = 1 18h 01h flash device interleave 1ah 20h cistpl_manfid 1ch 04h tpl_link (04h) 1eh 89h tplmid_manf: lsb 20h 00h tplmid_manf: msb 22h 03h 13h 23h 32h 2 mb - 100 ns 4 mb - 100 ns 8 mb - 100 ns 16 mb - 150 ns 24h 85h tplmid_card msb 26h 21h cistpl_funcid 28h 02h tpl_link 2ah 01h tplfid_function : memory 2ch 00h tplfid_sysinit address value description 2eh 12h cistpl_longlink_c 30h 04h tpl_link 32h 00h lowest byte 34h 00h 36h 02h 38h 00h highest byte 3ah 15h cistpl_vers1 3ch 40h tpl_link 3eh 05h tpllv1_major 40h 00h tpllv1_minor 42h 69h tpllv1_info i 44h 6eh n 46h 74h t 48h 65h e 4ah 6ch l 4ch 00h end text 4eh 56h v 50h 41h a 52h 4ch l 54h 55h u 56h 45h e 58h 20h space 5ah 53h s 5ch 45h e 5eh 52h r 60h 49h i 62h 45h e 64h 53h s 66h 20h space 68h 31h 1
imc002/004/008/016flsc e 18 preliminary address value description 6ah 30h 0 6ch 30h 0 6eh 20h space 70h 00h end text 72h 30h 30h 30h 31h 2 mb 4 mb 8 mb 16 mb 74h 32h 34h 38h 36h 2 mb 4 mb 8 mb 16 mb 76h 20h space 78h 00h end text 7ah 43h c 7ch 4fh o 7eh 50h p 80h 59h y 82h 52h r 84h 49h i 86h 47h g 88h 48h h 8ah 54h t 8ch 20h space 8eh 49h i 90h 4eh n 92h 54h t 94h 45h e 96h 4ch l 98h 20h space 9ah 43h c 9ch 4fh o 9eh 52h r address value description a0h 50h p a2h 4fh o a4h 52h r a6h 41h a a8h 54h t aah 49h i ach 4fh o aeh 4eh n b0h 20h space b2h 31h 1 b4h 39h 9 b6h 39h 9 b8h 35h 5 bah 00h end text bch ffh end of list beh 18h cistpl_jedec_c c0h 02h tpl_link c2h 89h manufacturer id c4h a6 2 mb (28f008s5) aa 4, 8, or 16 mb (28f016s5) c6h ffh cistpl_end c8h 00h invalid address
e imc002/004/008/016flsc 19 preliminary 7.0 system design considerations 7.1 power supply decoupling flash memory power-switching characteristics require careful device decoupling. system designers are interested in three supply current issues: standby, active and transient current peaks which are produced by rising and falling edges of ce 1 # and ce 2 #. the capacitive and inductive loads on the card and internal flash memory device pairs determine the magnitudes of these peaks. three-line control and proper decoupling capacitor selection suppress transient voltage peaks. the value series 100 cards contain on-card ceramic decoupling capacitors connected between v cc and gnd. the card connector should also have a 4.7 f electrolytic capacitor between v cc and gnd. the bulk capacitors overcome voltage slumps caused by printed-circuit-board trace inductance, and supply charge to the smaller capacitors as needed. 7.2 power-up/down protection the pcmcia/jeida-specified socket properly sequences the power supplies to the flash memory card via shorter and longer pins. each device in the memory card is designed to offer protection against accidental erasure or writing, caused by spurious system-level si gnals that may exist during power transitions. the card will power-up into the read state. a system desi gner must guard against active writes for v cc voltages above v lko (2.0 v). since both we# and ce 1 # must be low for a command write, driving either to v ih will inhibit writes. with its control register architecture, alteration of device contents only occurs after successful completion of the two-step command sequences. 7.3 rdy/bsy# and program/block erase polling rdy/bsy# is a full cmos output that provides a hardware method of detecting program and block erase completion. it transitions low time t whrl after a program or erase command sequence is written to a 28f0xxs5, and returns to v oh when all the wsm has finished executing the internal algorithm. rdy/bsy# can be connected to the interrupt input of the system cpu or controller. it is active at all times. rdy/bsy# is also v oh when the device is in erase suspend or deep power-down modes. 7.4 v cc , v pp , reset transitions and the command/status registers program and block erase completion are not guaranteed if the internally generated v pp drops below v pph . if the v pp status bit of the status register (sr.3) is set to 1, a clear status register command must be issued before further program/block erase attempts are allowed by the wsm. otherwise, the program (sr.4) or erase status (sr.5) bits of the status register will be set to 1s, if error is detected. reset transitions to v ih during program and block erase also abort the operations. data is partially altered in either case, and the command sequence must be repeated after normal operation is restored. device power-off, or reset transitions to v ih , clear the status register to initial value 10000xxx for the upper eight bits. the cui latches commands, as issued by system software, and is not altered by ce# transitions, or wsm actions. its state upon power-up, after exit from deep power-down or after v cc transitions below v lko , is read array mode. after program or block erase is complete, the cui must be reset to read array mode via the read array command, if access to the memory array is desired.
imc002/004/008/016flsc e 20 preliminary 8.0 electrical specifications 8.1 absolute maximum ratings* operating temperature during read............................ 0 c to +70 c (1) during write............................0 c to +70 c (1) storage temperature ................... C30 c to +80 c voltage on any pin with respect to ground........ C2.0 v to v cc +2.0 v (2) v cc supply voltage with respect to ground.................. C0.2 v to +7.0 v notice: this datasheet contains preliminary information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. * warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may effect device reliability. notes: 1. operating temperature is for commercial product defined by this specification. 2. minimum dc input voltage is C0.5 v; maximum dc voltage on output pins is v cc +0.5 v. 8.2 operating conditions temperature and v cc operating conditions symbol parameter min max units v cc supply voltage 4.75 5.25 v 8.3 capacitance (1) t a = +25 c, f = 1 mhz symbol parameter typ max unit condition c in address/control 25 50 pf c in v cc supply voltage 3 5 f c out output capacitance 25 50 pf note: 1. sampled, not 100% tested. output test points input 1.5 4.0v 0.0 1.5 0546_02 figure 2. transient input/output reference waveform for standard test configuration
e imc002/004/008/016flsc 21 preliminary 8.4 dc characteristics symbol parameter notes min max units test conditions i li input leakage current 1,2 20 m av cc = v cc max v in = v cc or gnd i lo output leakage current 1 20 m av cc = v cc max v out =v cc or gnd v il input low voltage 1 0 0.8 v v ih input high voltage 1 3.85 v cc + 0.5 v v ol output low voltage 1 0.4 v i ol = 3.2 ma v oh output high voltage 1 v cc C 0.4 v cc vi oh = C2.0 ma v lko v cc erase/program lock voltage 1 2.0 v notes: 1. values are the same for byte and word wide modes for all card densities. 2. exceptions: with v in = gnd, the leakage current on ce 1 #, ce 2 #, oe#, and we# will be < 500 m a due to internal pull-up resistors. with v in = v cc , rst leakage current will be < 150 m a due to internal pull-down resistors. 8.4 dc characteristics (continued) sym parameter density notes x16 mode units test conditions (mbytes) typ max i ccr v cc read current all 1, 3 75 ma v cc = v cc max t cycle = 100 ns i ccw v cc program current all 1, 3 150 ma i cce v cc erase current all 1, 3 100 ma i ccsl v cc sleep current 2, 4 1, 2, 4 30 170 m av cc = v cc max 8 1, 2, 4 30 200 m a reset, control signals = v ih 16 1, 2, 4 30 300 m a i ccs v cc standby current 2, 4 1, 2, 4 80 370 m av cc = v cc max 8 1, 2, 4 135 600 m a control signals = v cc 16 1, 2, 4 245 1,100 m a cmos test conditions: v il = gnd 0.2 v, v ih = v cc 0.2 v notes: 1. all currents are rms values unless otherwise specified. typical conditions: v cc = 5 v, t = +25 c. 2. control signals: ce 1 #, ce 2 #, oe#, we#. 3. characteristics assume only one pair of components are active and the remaining pairs are in standby. 4. inputs are either v cc 0.2 v or gnd 0.2 v.
imc002/004/008/016flsc e 22 preliminary 8.5 ac characteristics ac timing diagrams and characteristics are guaranteed to meet or exceed pcmcia 2.1 specifications. no delay occurs when switching between the common and attribute memory planes. 8.5.1 read operations common memory symbol parameter 2, 4, 8 mb 16 mb unit jedec pcmcia min max min max t avav t rc read cycle time 100 150 ns t avqv t a (a) address access time 100 150 ns t elqv t a (ce) card enable access time 100 150 ns t glqv t a (oe) output enable access time 50 75 ns t ehqx t dis (ce) output disable time from ce# 50 75 ns t ghqz t dis (oe) output disable time from oe# 50 75 ns t elqx t en (ce) output enable time from ce# 5 5 ns t glqx t en (oe) output enable time from oe# 5 5 ns t phqv power-down recovery to output delay. v cc = 5 v 530 530 ns
e imc002/004/008/016flsc 23 preliminary a4533-01 device and address selection outputs enabled power-up standby valid output address stable note 1 note 1 data valid standby v cc v cc power- down t ghqz t ehqz t avav t glqv t axqx high z high z v ih v il v ih v il v ih v il addresses(a) ce#(c) oe#(g) v ih v il we#(w) v oh v ol data(d/q) t elqv t elqx t avqv t glqx note 1: the filled area may be either high or low note 1 note 1 049102 figure 3. ac waveforms for read operations
imc002/004/008/016flsc e 24 preliminary 8.5.2 write operations common memory (1) symbol parameter 2, 4, 8 mb 16 mb unit jedec pcmcia min max min max t avav t c w write cycle time 100 150 ns t wlwh t w (we) write pulse width 60 80 ns t avwl t su (a) address setup time 10 20 ns t avwh t su (a-weh) address setup time for we# 70 100 ns t elwh t su (ceweh) card enable setup time for we# 70 100 ns t dvwh t su (d-weh) data setup time for we# 40 50 ns t whdx t h (d) data hold time 15 20 ns t whax t rec (we) write recovery time 15 20 ns t whrl we# high to rdy/bsy# ns t whgl t h (oe-we) output enable hold from we# 10 10 ns t phwl power-down recovery to we# going low 11 m s note: 1. read timing characteristics during erase and data program operations are the same as during read-only operations. refer to ac characteristics, read operations common memory .
e imc002/004/008/016flsc 25 preliminary addresses (a) ce# (e) oe# (g) we# (w) data (d/q) rp# ih v il v ih v il v ih v il v ih v il v il v in d in a in a valid srd in d whrl t high z whdx t ih v il v v (v) pp 12 3 4 6 5 pph v ih v ppl v avav t avwh t whax t dvwh t wlwh t qvvl t vpwh t in d avwl t whgl t whqv1,2 t elwh t phwl t rdy/bsy# (r) il v ih v oh v ol v 0491_03 notes: 1. v cc power-up and standby 2. write program or erase setup command 3. write valid address and program or erase confirm command 4. automated program or erase delay 5. read status register data 6. write read array command figure 4. ac waveforms for write operations
imc002/004/008/016flsc e 26 preliminary 8.5.3 power-up/power-down symbol parameter notes min max units pcmcia v i (ce) ce# signal level (0.0v < v cc < 2.0v) 1 0 v imax v ce# signal level (2.0v < v cc < v ih )1v cc C 0.1 v imax v ce# signal level (v ih < v cc )1v ih v imax v t su (v cc ) ce# setup time 20 ms t su (reset) ce# setup time 20 ms t rec (v cc ) ce# recover time 1.0 s t pr v cc rising time 2 0.1 300 ms t pf v cc falling time 2 3.0 300 ms t w (reset) reset width 10 s t h (hi-z reset) reset width 1 ms t s (hi-z reset) reset width 0 ms notes: 1. v imax means absolute maximum voltage for input in the period of 0.0 v < v cc < 2.0 v, v i (ce#) is only 0.00 v ~ v imax. 2. the t pr and t pf are defined as linear waveforms in the period of 10% to 90%, or vice-versa. even if the waveform is not a linear waveform, its rising and falling time must meet this specification. 049105 figure 5. power-up/down timing for systems supporting reset
e imc002/004/008/016flsc 27 preliminary 8.6 erase and data write performance (1,3) v cc = 5 v 0.5 v, t a = 0 c to +70 c sym parameter notes min typ (1) max units test conditions t whqv1 t ehqv1 word/byte program time 2,4 8 s 3 ms t whqv2 t ehqv2 block program time 2 0.4 2.1 sec word program mode block erase time 2 0.6 10 sec full chip erase time 2 38.4 sec notes: 1. +25 c, and normal voltages. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. to maximize system performance, the rdy/bsy# signal should be polled instead of using the maximum byte/word program time as a delay timer. the maximum word/byte program time is the absolute maximum time it takes the write algorithm to complete. the over- whelming majority of the bits program in the typical value specified.
imc002/004/008/016flsc e 28 preliminary 9.0 packaging a6887-01 w l c connector surface a surface b surface a x 2x s x x #34 #68 y #1 #35 2x t p 1 1 1 2 2 polarization key length 3 millimeters are in parenthesis () interconnect area tolerance = 0.002 substrate area tolerance = 0.004 c min 0.394 (10.0) l 0.008 3.370 (85.60) w 0.004 2.126 (54.0) p min 0.394 (10.0) s min 0.118 (3.0) t 0.065 (1.65) x 0.002 0.039 (1.00) y 0.002 0.063 (1.60) substrate area interconnect area
e imc002/004/008/016flsc 29 preliminary 10.0 ordering information imc008flsc, sbxxxxx where: i = intel mc = memory card 008 = density in megabytes (002, 004,008, 016 available) fl = flash technology s = blocked architecture c = revision sbxxxxx = customer identifier 11.0 additional information order number document 290597 5 volt flashfile? memory family; 28f004s5, 28f008s5, 28f016s5 datasheet 292177 ap-622 value series 100 card design 292204 ap-646 common flash interface (cfi) and command sets note 3 ap-606 interchangeability of series 1, series 2, and series 2+ flash memory cards notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. int ernational customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools. 3. these documents can be located at the intel world wide web support site, http://www.intel.com/support/flash/memory

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